1. Field of the Invention
The invention relates generally to automatic test equipment for testing electronic devices and more particularly to testing devices that operate with high speed digital signals.
2. Description of Related Art
Automatic test equipment (ATE) is widely used to test semiconductor components during the manufacturing process. The ATE, sometimes called a “tester,” generates stimulus signals and measures responses for a semiconductor device under test (DUT). The measured responses are compared to responses expected from a fully functioning device. The comparison between the measured response and expected response may be used to determine if the DUT is operating within design tolerances.
FIG. 1 shows a prior art test system in simplified block diagram form. The system includes tester body 100 and computer workstation 200. Computer workstation 200 provides a user interfaces and controls the operation of the tester body 100.
Within the tester body 100, there are multiple copies of circuitry called a channel. In FIG. 1, three channels, 110, 110-B, and 110-C, are shown. Each channel generates or measures a signal at one test point in time for the DUT. Each channel includes a pattern generator 120, timing generator 130, failure processor 140, formatter 150, driver 160, and comparator 170.
Pattern generator 120 stores a pattern that defines the data that is to be applied or is expected during each clock cycle of tester operation. The data specifies whether the tester is to drive data or measure data during each clock cycle. The pattern also includes information specifying the data value, such as logic 1 or logic 0 that is to be driven or is expected from a measurement.
To accommodate use of the test system with a variety of DUTs, which may represent 1's or 0's in different formats, the format of a test signal may be specified by a formatter 150. The formatter responds to format data that specifies how logical values, for example 0's and 1's, are to be driven or read from the DUT. For example, some devices represent a logic 1 by having a signal line at a high voltage during an entire cycle. Other devices represent a logic 1 by changing the state of the voltage at any point during a cycle. Still others represent a logical 1 by a voltage pulse during the cycle.
To provide signal transitions at the proper times, a channel includes a timing generator 130 that generates “edge” signals. Edge signals are signals that change state at a time programmed into the timing generator. The time transition occurs at any time between two tester cycles. A timeset is used to specify the specific time between the two tester cycles.
The edge signals are combined by the formatter 150 to produce an output signal having the desired shape with respect to voltage and time. For example, to create a pulse that starts 0.5 nanoseconds after the start of the cycle, and has a width of 1 nanoseconds, one of the edge signals would be programmed to occur 0.5 nanoseconds after the start of the cycle, and another edge signal would be programmed to occur at 1.5 nanoseconds after the start of the cycle. The formatter combines these signals to create the desired signal to be applied to driver 160. Driver 160 then produces the signal that is applied to the DUT. In this example, formatter 150 uses the first edge to define when driver 160 is turned ON and the second edge to define when driver 160 is turned OFF.
Traditionally, a formatter uses a circuit called an SR latch or SR flip-flop. An SR latch has a set port and a reset port. When a logic high signal is applied to the set port, the output, Q, of the latch is high. When a logic high signal is applied to the reset port, the output, Q, of the latch is low. When both ports receive a logic low signal, the output, Q, holds its state, and may be avoided in operation. Asserting the set and reset port simultaneously may lead to an indeterminate output state, and it is avoided in some implementations. However, U.S. Pat. No. 6,291,981 describes a latch with a deterministic output state in this scenario.
In a tester, format data from pattern generator 120 controls which edges are applied to the SR latch in each cycle. For example, in a cycle in which channel 110 should output a signal that goes high at 0.5 nanoseconds and low at 1.5 nanoseconds, format data that goes high at 0.5 nanoseconds is to be gated to the set port of the latch. Separately, specify that an edge that goes high at 1.5 nanoseconds is gated to the reset port of the latch.
Using multiple edge signals that can all be programmed to occur at different times, the tester can be programmed to generate a wide range of waveform formats.